 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| general description the max3570/max3571/max3573 low-cost, broad- band, dual-conversion tuner ics are designed for use in digital television receivers. each ic integrates all necessary rf functions, including an integrated hi-if filter, fully integrated vcos, and an integrated if vga. the operating frequency range extends from 50mhz to 878mhz while providing over 60db rf/if gain-control range. the max3570/max3571 have an if frequency centered at 44mhz, while the max3573 has an if out- put centered at 36mhz. these devices include a variable-gain front-end, achiev- ing an overall 8db noise figure. a dual synthesizer gen- erates both local oscillator (lo) frequencies, providing superior phase noise performance of -86dbc/hz at 10khz. the integrated hi-if filter achieves 55dbc (typ) of image rejection. only an if saw filter, passive loop fil- ters, and a crystal are needed to complete a single-chip tuner. device programming and configuration are accomplished with a 3-wire serial interface for the max3570, and with a 2-wire serial interface for the max3571/max3573. the max3570/max3571/max3573 are available in a 48-pin qfn-ep package and are specified for the com- mercial (0? to +70?) temperature range. applications dvb-c digital terrestrial receivers atsc digital terrestrial receivers cable modems docsis/euro docsis cable modems itu j.83 digital set-top boxes features ? fully integrated hi-if filter ? fully integrated vcos, no external components or traces ? low 8db noise figure ? high linearity?reater than 54dbc, cso, ctb, x-mod ? industry? smallest footprint ? superior phase noise for 256-qam, 8-vsb, and cofdm max3570/max3571/max3573 hi-if single-chip broadband tuners ________________________________________________________________ maxim integrated products 1 max3570 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v cc v cc v cc rfin+ rfin- gnd gnd tune1 locflt1 gnd i.c. scl sda v cc v cc i.c. div/ld cpout1 oscout oscin gnd gnd tune2 locflt2 gnd cpout2 v cc v cc v cc v cc ifout2+ ifvga ifin- ifin+ v cc v cc v cc ifout2- gnd gnd ifout1- ifout1+ gnd lnabias bias gnd rfvga hi-if filter 3-wire serial interface dual synthesizer cs pin configurations/ functional diagrams ordering information 19-0067; rev 0; 2/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max3570 cgm 0 c to +70 c 48 qfn-ep* max3571 cgm 0 c to +70 c 48 qfn-ep* max3573 cgm 0 c to +70 c 48 qfn-ep* * ep = exposed paddle. pin configurations/functional diagrams continued at end of data sheet. part serial interface if center frequency (mhz) max3570 3-wire 44 max3571 2-wire 44 max3573 2-wire 36 selector guide evaluation kit available
max3570/max3571/max3573 hi-if single-chip broadband tuners 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ...........................................................-0.3v to +5.5v ifin_, ifout1_, ifout2_, rfin_, tune_, locflt_, cpout_, oscin, oscout, ifvga, rfvga, bias, lnabias, addr_, cs , scl, sda, div/ld...............-0.3v to (v cc + 0.3v) continuous power dissipation (t a = +70?) 48-pin qfn (derate 27mw/? above +70?) ............2162mw operating temperature range...............................0? to +70? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? dc electrical characteristics (max357_ ev kit, v cc = +4.75v to +5.25v, r bias = 5.9k ? ?%, no ac signal applied, t a = 0? to +70?, unless otherwise noted. typical values are at v cc = +5.0v, t a = +25?, unless otherwise noted.) (note 1) parameter conditions min typ max units supply voltage and supply current supply voltage 4.75 5.25 v at t a = +25 c, v rfvga = +3.0v 320 supply current at t a = +70 c, v rfvga = +0.5v 385 ma rf and if vga input bias current v rfvga = v ifvga = +0.5v and +3.0v -50 +50 ? maximum gain 3 rf and if vga control voltage minimum gain 0.5 v logic interface input-logic low (v il ) 0.9 v input-logic high (v ih ) 2.3 v input logic current -10 +10 ? output-logic low sink current = 3ma 0.4 v output-logic high source current = 3ma 2.8 v caution! esd sensitive device max3570/max3571/max3573 hi-if single-chip broadband tuners _______________________________________________________________________________________ 3 ac electrical characteristics (max357_ ev kit, v cc = +4.75v to +5.25v, r bias = 5.9k ? ?%, inputs terminated to 75 ? , f rfin = 50mhz to 878mhz, f if = 45.75mhz (max3570/max3571), f if = 38.9mhz (max3573), f comp1 = 1mhz, f comp2 = 62.5khz, t a = 0? to +70?, unless other- wise noted. typical values are at v cc = +5.0v, t a = +25?, unless otherwise noted.) (note 1) parameter conditions min typ max units overall requirements (rf input to 1st if output) operating frequency range gain specification met across this frequency band 50 878 mhz input return loss worst case across band, 75 ? , any rfvga setting 8 db t a = +25? 31.5 38.5 45.0 voltage gain z source = 75 ? , z load = 200 ? , v rfvga = +3.0v t a = +70? 30.0 37 43.5 db gain-reduction range measured at 50mhz 30 db v rfvga = +3.0v at f rfin = 878mhz vs. 50mhz -1.5 +1.5 gain flatness v rfvga = 0.5v at f rfin = 878mhz vs. 50mhz -2 +2 db noise figure v rfvga = +3.0v 7.9 db v rfvga = +3.0v, t a = +25 c to +70 c, v cc = 4.85v to 5.15v, f rf = 860mhz 34 iip2 at 12db gain reduction, t a = +25 c to +70 c, v cc = 4.85v to 5.15v, f rf = 860mhz 52.5 dbm v rfvga = +3.0v, t a = +25 c to +70 c, v cc = 4.85v to 5.15v +8 iip3 at 12db gain reduction, t a = +25 c to +70 c, v cc = 4.85v to 5.15v +18 dbm beats within output 0dbmv pix carrier level (note 2) -48 dbc channel flatness from pix to (pix + 4) mhz -0.5 +0.3 +1.0 db isolation 5m hz to 150m h z, rf i np ut to if output (n ote 3) -63 -68 dbc measured at 91mhz above desired pix (max3570/max3571) 50 55 image rejection measured at 77.75mhz above desired pix (max3573) 50 55 dbc 50mhz to 878mhz -54 -48 spurious at rf input (note 3) above 878mhz (lo and lo harmonics) +3 dbmv f offset = 1khz -62 f offset = 10khz, bw loop = 2.5khz -86 single sideband phase noise f offset = 100khz, bw loop = 2.5khz -105 dbc/hz output return loss balanced, 50 ? 9db max3570/max3571/max3573 hi-if single-chip broadband tuners 4 _______________________________________________________________________________________ ac electrical characteristics (max357_ ev kit, v cc = +4.75v to +5.25v, r bias = 5.9k ? ?%, inputs terminated to 1k ? , z load = 300 ? , f if = 40mhz to 48mhz , t a = 0? to +70?, unless otherwise noted. typical values are at v cc = +5.0v, t a = +25?, unless otherwise noted.) (note 1) parameter conditions min typ max units second if stage input impedance balanced 1.7 k ? output impedance balanced (note 3) 100 ? z source = 1.1k ? , z load = 300 ? , v ifvga = +3.0v 50 53 57 passband voltage gain v ifvga = +0.5v 14.5 23 db passband flatness from pix to (pix - 4) mhz for 45.75mhz pix frequency (note 3) 0.2 db maximum output voltage 3.2 v p-p vga gain slope v ifvga = +3.0v to +0.5v 10 20 db/v -3db bandwidth (note 3) 180 mhz noise figure f if = 44mhz, v ifvga = +3.0v 5.1 db noise figure vs. attenuation first 10db back-off 0.3 db/db gain = 45db, v out = 1.5v p-p -27.5 iip3 gain = 27db, v out = 1.5v p-p -11.3 dbm oip3 v out = 1.5v p-p , v ifvga = +3.0v to +0.5v (note 3) 25 dbm psrr 50mv p-p at 200khz -57 db max3570/max3571/max3573 hi-if single-chip broadband tuners _______________________________________________________________________________________ 5 synthesizer electrical characteristics (max357_ ev kit, v cc = +4.75v to +5.25v, r bias = 5.9k ? ?%, f comp1 = 1mhz, f comp2 = 62.5khz, t a = 0? to +70?, unless oth- erwise noted. typical values are at v cc = +5.0v, t a = +25?, unless otherwise noted.) (note 1) parameter conditions min typ max units 1st local oscillator (lo1) tuning range 1274 2111 mhz vco tuning gain 40 120 mhz/v 1st local oscillator (lo1) divider rf1 n-divider ratio 256 8191 rf1 r-divider ratio 131 1st local oscillator (lo1) phase detector and charge pump phase-detector phase noise f offset = 2khz (note 3) -142 dbc charge-pump source/sink matching correlate locked vs. unlocked 6 % charge-pump tri-state current rf1 -7 +7 na 2nd local oscillator (lo2) tuning range 1175 1193 mhz vco tuning gain 25 70 mhz/v 2nd local oscillator (lo2) divider rf2 n-divider ratio 512 65,535 rf2 r-divider ratio 2 127 2nd local oscillator (lo2) phase detector and charge pump phase-detector phase noise f offset = 2khz (note 3) -142 dbc charge-pump source/sink matching correlate locked vs. unlocked 6 % charge-pump tri-state current rf2 -7 +7 na logic interface (max357_ ev kit, v cc = +4.75v to +5.25v, r bias = 5.9k ? ?%, t a = 0? to +70?, unless otherwise noted.) (note 1) parameter conditions min typ max units maximum clock frequency 400 khz note 1: these parameters are production tested from t a = +25? to +70?, and are guaranteed by design and characterization at t a = 0?. note 2: when using the tuning table provided in the ev kit documentation. note 3: these parameters are guaranteed by design and characterization, and are not production tested. max3570/max3571/max3573 hi-if single-chip broadband tuners 6 _______________________________________________________________________________________ t ypical operating characteristics (max357_ ev kit, v cc = +5.0v, r bias = 5.9k ? , f rf = 860mhz, f if = 44mhz (max3570/max3571), 36mhz (max3573), t a = +25?, unless otherwise noted.) 300 320 340 360 380 400 25 40 45 30 35 50 55 60 65 70 supply current vs. temperature max3570/71/73 toc01 temperature ( c) supply current (ma) 12db attentuation maximum gain -20 0 -10 20 10 40 30 50 01.0 1.5 0.5 2.0 2.5 3.0 voltage gain vs. rfvga voltage max3570/71/73 toc02 rfvga voltage (v) voltage gain (db) 36 39 38 37 40 voltage gain vs. supply voltage max3570/71/73 toc03 supply voltage (v) voltage gain (db) 4.75 4.85 4.95 5.05 5.15 5.25 850mhz 50mhz 450mhz voltage gain vs. frequency (max gain) max3570/71/73 toc04 frequency (mhz) voltage gain (db) 650 450 250 37 36 35 38 39 40 41 34 50 850 t a = +25 c t a = +70 c t a = +55 c voltage gain vs. frequency (max -12db) max3570/71/73 toc05 frequency (mhz) voltage gain (db) 650 450 250 23 24 25 26 27 28 29 22 50 850 t a = +25 c t a = +70 c t a = +55 c 7.0 8.0 7.5 9.0 8.5 9.5 10.0 50 450 250 650 850 noise figure vs. frequency max3570/71/73 toc06 frequency (mhz) noise figure (db) t a = +70 c t a = +25 c t a = +55 c noise figure vs. voltage gain max3570/71/73 toc07 voltage gain (db) noise figure (db) 37 35 33 31 10 12 14 16 18 20 8 29 39 t a = +70 c t a = +55 c t a = +25 c -150 -120 -130 -140 -110 -100 -90 -80 -70 -60 -50 100 10k 1k 100k 1m 10m phase noise vs. offset frequency max3570/71/73 toc08 frequency (hz) phase noise (dbc/hz) -40 -30 -10 -20 0 10 ifout1 frequency response max3570/71/73 toc09 if frequency (mhz) amplitude (db) 050 100 150 max3570/max3571 max3573 max3570/max3571/max3573 hi-if single-chip broadband tuners _______________________________________________________________________________________ 7 -9.5 -8.0 -8.5 -9.0 -7.5 rfin input return loss max3570/71/73 toc10 rf frequency (mhz) return loss (db) 50 250 450 650 850 30 40 35 50 45 55 60 19 29 24 34 39 input ip2 vs. voltage gain max3570/71/73 toc11 voltage gain (db) input ip2 (dbm) t a = +25 c t a = +55 c t a = +70 c 3 8 18 13 23 28 input ip3 vs. voltage gain max3570/71/73 toc12 voltage gain (db) input ip3 (dbm) 19 29 24 34 39 t a = +55 c t a = +25 c t a = +70 c ifvga voltage gain vs. ifvga voltage max3570/71/73 toc13 ifvga voltage (v) ifvga voltage gain (db) 2.8 2.3 1.8 1.3 0.8 15 20 25 30 35 40 45 50 55 60 10 0.3 3.3 ifvga voltage gain vs. if frequency max3570/71/73 toc14 if frequency (mhz) ifvga voltage gain (db) 100 10 42 44 46 48 50 52 54 56 58 40 1 1000 t a = +55 c t a = +70 c t a = +25 c ifvga noise figure vs. ifvga voltage max3570/71/73 toc15 ifvga voltage (v) noise figure (db) 3.0 2.7 2.4 2.1 1.8 1.5 1.2 0.9 10 15 20 25 30 5 0.6 3.3 t a = +70 c t a = +55 c t a = +25 c ifvga input ip3 vs. ifvga voltage max3570/71/73 toc16 ifvga voltage (v) input ip3 (dbm) 2.8 2.3 1.8 1.3 0.8 -35 -30 -25 -20 -15 -10 -5 -40 0.3 3.3 t a = +25 c t a = +55 c t a = +70 c t ypical operating characteristics (continued) (max357_ ev kit, v cc = +5.0v, r bias = 5.9k ? , f rf = 860mhz, f if = 44mhz (max3570/max3571), 36mhz (max3573), t a = +25?, unless otherwise noted.) max3570/max3571/max3573 hi-if single-chip broadband tuners 8 _______________________________________________________________________________________ pin description pin name function 1v cc rf variable-gain amplifier (vga) supply voltage. bypass with a capacitor as close to the pin as possible. do not share the bypass capacitor ground vias with any other branches. 2, 3 rfin+, rfin- differential lna inputs. requires ac coupling and can be driven balanced or single-ended. recommend driving pin 3 and ac ground pin 2 for optimum input ip2 performance. 4, 6, 10, 20, 23, 24, 28, 32, 34, 45 gnd ground. connect to pc board ground plane. 5v cc 1st mixer supply voltage. bypass with a capacitor as close to the pin as possible. do not share the bypass capacitor ground vias with any other branches. 7v cc 1st vco circuitry supply voltage. bypass with a capacitor as close to the pin as possible. do not share the bypass capacitor ground vias with any other branches. 8 tune1 1st vco tuning input. connect this analog voltage input to a third-order loop-filter output. 9 locflt1 1st lo noise-filtering capacitor connection. connect a capacitor to gnd. (refer to the ev kit.) i.c. internal connection. leave this pin unconnected (max3570). 11 addr2 2-wire serial interface 2nd address pin (max3571/max3573) cs 3-wire serial interface enable input pin (spi /qspi /microwire compatible) (max3570) 12 addr1 2-wire serial interface 1st address pin (max3571/max3573) 3-wire serial interface clock input pin (spi/qspi/microwire compatible) (max3570) 13 scl 2-wire serial interface clock input pin (max3571/max3573) 3-wire serial interface data input pin (spi/qspi/microwire compatible) (max3570) 14 sda 2-wire serial interface data input pin (max3571/max3573) 15 v cc digital circuitry supply voltage. bypass with a capacitor as close to the pin as possible. do not share the bypass capacitor ground vias with any other branches. 16 div/ld divider or lock-detect logic output 17 i.c. internal connection. leave this pin unconnected. 18 cpout1 1st pll charge-pump output. connect this high-impedance current output to a third-order loop-filter input. 19 v cc 1st synthesizer supply voltage. bypass with a capacitor as close to the pin as possible. do not share the bypass capacitor ground vias with any other branches. 21 oscout reference oscillator buffered output 22 oscin reference oscillator input. connect an external reference oscillator or crystal to this analog input through a coupling capacitor. 25 v cc 2nd synthesizer supply voltage. bypass with a capacitor as close to the pin as possible. do not share the bypass capacitor ground vias with any other branches. 26 cpout2 2nd p ll c har g e- p um p outp ut. c o nnect thi s hi g h- i m p ed ance cur r ent outp ut to a thi r d - or d er l oop - fi l ter i np ut. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. max3570/max3571/max3573 hi-if single-chip broadband tuners _______________________________________________________________________________________ 9 pin name function 27 v cc 2nd charge-pump supply voltage. bypass with a capacitor as close to the pin as possible. do not share the bypass capacitor ground vias with any other branches. 29 locflt2 2nd lo noise-filtering capacitor connector. connect a capacitor to gnd. (refer to the ev kit.) 30 tune2 2nd vco tuning input. connect this analog voltage input to a third-order loop-filter output. 31 v cc 2nd vco circuitry supply voltage. bypass with a capacitor as close to the pin as possible. do not share the bypass capacitor ground vias with any other branches. 33 v cc 2nd lo generation supply voltage. bypass with a capacitor as close to the pin as possible. do not share the bypass capacitor ground vias with any other branches. 35, 36 ifout1+, ifout1- 1st differential if outputs. these outputs are ac-coupled to the saw filter inputs. 37 v cc 2nd mixer and 1st if amplifier circuit supply voltage. bypass with a capacitor as close to the pin as possible. do not share the bypass capacitor ground vias with any other branches. 38, 39 ifin+, ifin- differential if inputs. connected to the saw filter outputs. 40 ifvga if vga control. see the typical operating characteristics . 41 v cc if vga supply voltage. bypass with a capacitor as close to the pin as possible. do not share the bypass capacitor ground vias with any other branches. 42, 43 ifout2+, ifout2- if vga outputs 44 v cc hi-if filter circuit supply voltage. bypass with a capacitor as close to the pin as possible. do not share the bypass capacitor ground vias with any other branches. 46 bias bias resistor connection. connect a 5.9k ? precision 1% resistor to gnd. resistor value can be increased to decrease the nominal current at the expense of linearity. refer to application note: max3570/max3571/max3573 bias resistor setting for further information. 47 rfvga rf vga control. see the typical operating characteristics . 48 lnabias lna bias input. connect through an inductor to gnd. (refer to the ev kit.) ep gnd exposed ground paddle. dc and ac gnd return for the ic. connect to pc board ground plane using multiple vias. pin description (continued) max3570/max3571/max3573 detailed description programmable registers the max3570/max3571/max3573 include nine pro- grammable registers (registers 1?) consisting of six divider registers (registers 1?), one vco control register (register 7), and one test register (register 8). the final register (register 9) controls the hi-if filter frequency off- set, as well as the div/ld output mux status. most regis- ters contain some don? care (x) bits. these can be either a ??or a ??and do not affect the mode of opera- tion (table 1). data is shifted in msb first. positive logic is used. 3-wire serial interface the max3570 uses a 3-wire spi/qspi/microwire- compatible serial interface. an active-low chip select ( cs ) enables the device to receive data from the serial input (sda). register address and data information are clocked in on the rising edge of the serial clock signal (scl). while shifting in the serial data, the device remains in its original configuration. a rising edge on cs latches the data into the max3570? internal regis- ter, initiating the device? change of state. figure 1 shows the details of the 3-wire interface address and data configuration. 2-wire serial interface the max3571/max3573 use a 2-wire i 2 c*-compatible serial interface. the serial bus is monitored continuous- ly, waiting for a start condition followed by its address. the address has 5 msb internally set, while the next two bits are set with external pins, addr2 and addr1. the lsb determines whether it is a read or write. when the device recognizes its address, it acknowledges by pulling the sda line low for one clock period; it is then ready to accept the register address for the first byte of data. another acknowledge (ack) is sent once the register address is received. the device is then ready to accept the data byte. more data bytes can be sent for sequential registers, and ack is sent after each byte. after the final ack is sent, the master issues a stop condition to free the bus. figure 2 shows the details of the 2-wire interface structure. there is only one read-back register in the max3571/max3573. to access it, send a start condi- tion, and then the read address is set by the external addr2 and addr1 pins. an ack is sent, and the mas- ter then begins to read from the slave. after the eight bits have been read, the master should issue a no- acknowledge (nack), and then a stop condition. hi-if single-chip broadband tuners 10 ______________________________________________________________________________________ msb lsb 4 address bits 8 data bits a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 figure 1. 3-wire serial interface address and data configuration device address register address data data start 8b11000 max3570/max3571/max3573 hi-if single-chip broadband tuners ______________________________________________________________________________________ 11 msb lsb 8 data bits register number register name register address d7 d6 d5 d4 d3 d2 db1 d0 1 vco1_n1 00 hex xxx 1n12 1n11 1n10 1n9 1n8 2 vco1_n2 01 hex 1n7 1n6 1n5 1n4 1n3 1n2 1n1 1n0 3 vco1_r 02 hex xxx1r4 1r3 1r2 1r1 1r0 4 vco2_n1 03 hex 2n15 2n14 2n13 2n12 2n11 2n10 2n9 2n8 5 vco2_n2 04 hex 2n7 2n6 2n5 2n4 2n3 2n2 2n1 2n0 6 vco2_r 05 hex x 2r6 2r5 2r4 2r3 2r2 2r1 2r0 7 vco_set 06 hex 1vco2 1vco1 1vco0 x 1cp1 1cp0 2cp1 2cp0 8 test 07 hex x 1t4 1t3 1t2 1t1 1t0 st1 st0 9 hi-if 08 hex xxf1 f0 mux3 mux2 mux1 mux0 table 2. register configuration x = don? care. register number register name register address function 1 vco1_n1 00 hex vco1 n-divider high 2 vco1_n2 01 hex vco1 n-divider low 3 vco1_r 02 hex vco1 r-divider 4 vco2_n1 03 hex vco2 n-divider high 5 vco2_n2 04 hex vco2 n-divider low 6 vco2_r 05 hex vco2 r-divider 7 vco_set 06 hex vco select and charge-pump settings 8 test 07 hex test mode. for test purposes only. program to 20 hex . 9 hi-if 08 hex mode select, mux output select table 3. register description bit id bit name bit location (0 = lsb) function xx 7, 6, 5 reserved 1n 1st vco n-divider 4? 1st vco n-divider msb bits table 4. 1st vco n-divider higher register (vco1_n1) bit id bit name bit location (0 = lsb) function 1n 1st vco n-divider 7? 1st vco n-divider lsb bits table 5. 1st vco n-divider lower register (vco1_n2) max3570/max3571/max3573 hi-if single-chip broadband tuners 12 ______________________________________________________________________________________ bit id bit name bit location (0 = lsb) function xx 7, 6, 5 reserved 1r 1st vco r-divider 4? 1st vco r-divider table 6. 1st vco r-divider higher register (vco1_r) bit id bit name bit location (0 = lsb) function 2n 2nd vco n-divider 7? 2nd vco n-divider msb bits table 7. 2nd vco n-divider higher register (vco2_n1) bit id bit name bit location (0 = lsb) function 2n 2nd vco n-divider 7? 2nd vco n-divider lsb bits table 8. 2nd vco n-divider lower register (vco2_n2) bit id bit name bit location (0 = lsb) function xx 7 reserved 2r 2nd vco r-divider 6? 2nd vco r-divider table 9. 2nd vco r-divider higher register (vco2_r) bit id bit name bit location (0 = lsb) function 1vco 1st vco tank select 7, 6, 5 1st vco tank select: ?000 = 1st vco tank (the lowest frequency oscillator) ?001 = 2nd vco tank ?010 = 3rd vco tank ?011 = 4th vco tank ?100 = 5th vco tank ?101 = 6th vco tank ?110 = 7th vco tank ?111 = 8th vco tank (the highest frequency oscillator) xx 4 reserved 1cp 1st vco charge-pump current 3, 2 1st vco charge-pump current: ?00 = 0.2ma ?01 = 0.4ma ?10 = 0.6ma ?11 = 0.8ma 2cp 2nd vco charge-pump current 1, 0 2nd vco charge-pump current: ?00 = 0.2ma ?01 = 0.4ma ?10 = 0.6ma ?11 = 0.8ma table 10. vco tank and charge-pump select register (vco_set) max3570/max3571/max3573 hi-if single-chip broadband tuners ______________________________________________________________________________________ 13 bit id bit name bit location (0 = lsb) function xx 7, 6 reserved f hi-if filter control 5, 4 hi-if filter control: ?00 = step down 5mhz ?01 = nominal ?11 = step up 5mhz mux lock-detect and mux output control 3? lock-detect and mux output control: ?0000 = normal, low-noise operation ?0001 = lock detect for the 1st vco ?0010 = lock detect for the 2nd vco ?0011 = 1st vco n-divider ?0100 = 1st vco r-divider ?0101 = 2nd vco n-divider ?0110 = 2nd vco r-divider ?0111 = reference oscillator ?1000 = and output of lock detector ?1001 = nand output of lock detector ?1010 = 1st vco v tune over/under indicator ?1011 = 2nd vco v tune over/under indicator table 11. hi-if step control and mux output register (hi-if) msb lsb 8 data bits register number register name d7 d6 d5 d4 d3 d2 db1 d0 1 ld_por lock1 lock2 por ou1 ou2 x x x table 12. read mode register configuration bit id bit name bit location (0 = lsb) function lock1 lock1 7 lock indicator for 1st vco (see table 15) lock2 lock2 6 lock indicator for 2nd vco por por 5 power-on reset indicator; 1 indicates successful power-on reset ou1 ou1 4 over or under v tune indicator for 1st vco (see table 15) ou2 ou2 3 over or under v tune indicator for 2nd vco xx 2, 1, 0 reserved table 14. lock detect and por register register number register name function 1 ld_por lock detect and power-on reset table 13. read mode register description lock1 ou1 description 1x 1st vco locked 00( under ) choose next lower tank 01 (over) choose next higher tank table 15. 1st vco truth table max3570/max3571/max3573 hi-if single-chip broadband tuners 14 ______________________________________________________________________________________ max3570 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v cc v cc v cc rfin+ rfin- gnd gnd tune1 locflt1 gnd i.c. scl sda v cc i.c. v cc div/ld cpout1 oscout oscin gnd gnd tune2 locflt2 gnd cpout2 v cc v cc v cc v cc ifout2+ ifvga ifin- ifin+ v cc v cc v cc ifout2- gnd gnd ifout1- ifout1+ gnd lnabias bias gnd rfvga hi-if filter 3-wire serial interface dual synthesizer cs serial interface from dac if output to adc from dac rf input t ypical application circuit applications information rf input an lna provides a single-ended broadband input matched to a 75 ? source. it provides a linear, continu- ous gain-control range of over 30db before the signal is upconverted. a 16nh inductor in series with a 1000pf capacitor is required at the rf input (pin 3) to achieve optimal matching (see the typical application circuit ). hi-if frequency agility in a double conversion receiver, beat frequencies are generated from harmonics of the los associated with this system. in some instances these beat frequencies may coincide with the if. if this occurs, it is possible to shift the hi-if slightly by retuning the los. this shift moves the beat out of the if band. the max3570/ max3571/max3573 support this capability by allowing the user to shift the center frequency of the hi-if filter slightly, tracking the shift in the lo frequencies, pre- serving the optimum image rejection and insertion loss. the hi-if filter frequency shift is controlled with the hi- if filter step control bits (f0 and f1, register address 8). (patent pending.) if outputs a first differential if output (ifout1+, ifout1-), although intended to drive a standard if saw filter, is capable of driving loads as low as 200 ? . a second dif- ferential if output (ifout2+, ifout2-) provides a bal- anced output capable of driving loads as low as 300 ? and can be ac-coupled to a standard qam demodula- tor? adc. gain control the max3570/max3571/max3573 have two vga cir- cuits that are used to achieve the optimum snr while minimizing distortion. at low input signal levels the rfvga voltage should be 3.0v. this sets the lna gain at its maximum. the ifvga control voltage is used to set the required output signal level. as the rf input level increases, the ifvga voltage drops. when the ifvga voltage reaches a user-defined value (rfvga attack point), the ifvga voltage is frozen and the rfvga volt- age is adjusted to maintain the desired output level. vco1 selection vco1 generates the first local oscillator (lo1) frequen- cy for the upconverting mixer. it consists of an array of eight vcos; each tuned to a unique frequency band, to cover the required frequency range. the desired vco is chosen through the serial data interface (sdi). please refer to application note: max3550/max3551/ max3553 vco selection for further information on vco1 vco selection. synthesizer comparison frequency selection the two on-chip synthesizers of the max3570/max3571/ max3573 are capable of supporting a wide range of comparison frequencies. the pll for the first lo (lo1) provides a comparison frequency range from below 250khz up to 4mhz, assuming a 4mhz reference (crys- tal) frequency. the second lo (lo2) pll supports a comparison frequency range from below 50khz up to 2mhz, again assuming a 4mhz reference. comparison frequencies of 1mhz for lo1 (r1 = 4) and 250khz for lo2 (r2 = 16) are recommended for the max3570 and max3571. for the max3573, the recom- mended lo2 comparison frequency is 142.8571khz (r2 = 28, 4mhz crystal frequency). these values ensure opti- mum resolution while working with the loop filters to sup- press spurious energy and provide acceptable lock time. synthesizer loop filters a third-order lowpass loop filter is used for each local oscillator to achieve low spurious and low phase noise. the loop bandwidth is chosen so the spurious rejection is sufficient and a reasonable lock time is achieved. refer to the ev kit for the recommended loop-filter com- ponent values. crystal oscillator interface the crystal oscillator pins (oscin, oscout) must be connected to a crystal or an external reference oscilla- tor. when connecting directly to a crystal, refer to the ev kit for the recommended component values. when using an external reference oscillator, drive oscin with an amplitude of 1.5v p-p , and leave oscout uncon- nected. power-supply layout to minimize coupling between different sections of the ic, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at a central v cc node. the v cc traces branch out from this node, each going to a separate v cc node in the max3570/max3571/ max3573 circuit. at the end of each trace is a bypass capacitor with a low impedance to ground at the frequen- cy of interest. this arrangement provides local decoupling at each v cc pin. use at least one via per bypass capaci- tor for a low-inductance ground connection. max3570/max3571/max3573 hi-if single-chip broadband tuners ______________________________________________________________________________________ 15 max3570/max3571/max3573 hi-if single-chip broadband tuners 16 ______________________________________________________________________________________ max3571 max3573 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v cc v cc v cc rfin+ rfin- gnd gnd tune1 locflt1 gnd scl sda v cc i.c. v cc div/ld cpout1 oscout oscin gnd gnd tune2 locflt2 gnd cpout2 v cc v cc v cc v cc ifout2+ ifvga ifin- ifin+ v cc v cc v cc ifout2- gnd gnd ifout1- ifout1+ gnd lnabias bias gnd rfvga hi-if filter 2-wire serial interface dual synthesizer addr1 addr2 pin configurations/ functional diagrams (continued) chip information transistor count: 18,970 process: sige bicmos matching network layout the layout of a matching network can be very sensitive to parasitic circuit elements. to minimize parasitic inductance, keep all traces short and place compo- nents as close to the ic as possible. to minimize para- sitic capacitance, a cutout in the ground plane (and any other planes) below the matching network compo- nents can be used. refer to the ev kit for the recom- mended input matching network. max3570/max3571/max3573 hi-if single-chip broadband tuners maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 17 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) refer to g4877-1. 32, 44, 48l qfn.eps h 1 2 21-0092 package outline 32,44,48l qfn, 7x7x0.90 mm u h 2 2 21-0092 package outline, 32,44,48l qfn, 7x7x0.90 mm |
Price & Availability of MAX3573CGM
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |